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VERILOG VARIANTS

Electrical Sciences

ECE DEPARTMENT VLSI LAB

May 19, 2022
10 a.m.

General Event Fee

9655455663

₹3000

3 Hours

Verilog Variants is an event that mainly focuses on stimulating the programmer's ability to code and debug the VHDL programs. It is a single-day event, with a maximum of 2 to 3 hours. This event contains 2 rounds. The first round is "Quiz" and the second round is "Coding and Debugging". 

ROUND 1: Quiz 
ROUND 2: Debugging 
It is a one-day event, the timings are 10 am to 11 am and 2 pm to 3.30 pm 
Here we have two rounds.
1. Quiz
2. Debugging 
The basics about Verilog are more than enough to bag up the prizes!

Rules 
1. Use of Mobile Phones and cameras is not permitted.
2. Makeup to the given time slots.
3. Avoid Malpractice
4. Handle the event equipment with care
5. Keep up to the allotted time.   

 

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