Verilog Variants is an event that mainly focuses on stimulating the programmer's ability to code and debug the VHDL programs. It is a single-day event, with a maximum of 2 to 3 hours. This event contains 2 rounds. The first round is "Quiz" and the second round is "Coding and Debugging".
It is a one-day event, the timings are 10 am to 11 am and 2 pm to 3.30 pm
Here we have two rounds.
1. Quiz
2. Debugging
The basics about Verilog are more than enough to bag up the prizes!
Rules
1. Use of Mobile Phones and cameras is not permitted.
2. Makeup to the given time slots.
3. Avoid Malpractice
4. Handle the event equipment with care
5. Keep up to the allotted time.
